1. Field of the Invention
The present invention relates to a configuration of a transport stream decoder for extracting a transport stream (hereinafter referred to as TS) in a digital broadcasting receiving device, and to a configuration of the digital broadcasting receiving device using the transport stream decoder.
2. Description of the Background Art
In addition to BS and CS digital broadcasting for which actual broadcasting has already been started, CS digital broadcasting at 110 degrees east longitude, terrestrial digital broadcasting and the like have been attempted for practical use. Accordingly, a digital broadcasting receiving device that receives such digital broadcasting is required to handle a plurality of transport streams.
Moreover, in a system for receiving digital broadcasting, transport streams may be supplied from media other than broadcasting, for example, a recording medium such as a video tape decoder or hard disk (HDD).
Configuration of Conventional Digital Broadcasting Receiving Device 2000
FIG. 6 is a schematic block diagram showing an extracted principle portion of the configuration of conventional digital broadcasting receiving device 2000.
Referring to FIG. 6, in digital broadcasting receiving device 2000, a RF signal received by an antenna (not shown) is tuned by tuners 100.1 and 100.2, and the tuned signals are applied to 8PSK demodulators 102.1 and 102.2, respectively.
Demodulated signals from 8PSK demodulators 102.1 and 102.2 are applied to transport stream decoders (hereinafter referred to as TS decoders) 104.1 and 104.2, respectively, and are then applied to an MPEG-AV decoder 110 via a switch 106. Thus, in the circuitry from TS decoders 104.1 and 104.2, a baseband signal is extracted from a tuned channel.
It is noted that, though FIG. 6 shows 8PSK as an example of a modulation demodulation system, the modulation demodulation system is not particularly limited thereto.
MPEG-AV decoder 110 receives data streams provided by switch 106, and uses a random access memory (hereinafter referred to as RAM) 112 as a buffer for temporarily storing data. Then, the data streams are converted into video and audio signals.
Here, two systems, i.e. a system from tuner 100.1 to TS decoder 104.1 and a system from tuner 100.2 to TS decoder 104.2, are provided as described above in order to, for example, receive data to be stored into a storage device, which will be described later, in the background, even during the period in which the video and audio signals selected by a user are displayed on a display device (not shown).
Digital broadcasting receiving device 2000 further includes an integrated storage device 148 receiving signals from TS decoders 104.1 and 104.2 via a data bus BS1 and storing the signals; a central processing unit (CPU) 144 performing a predetermined process on the data stored in integrated storage device 148 and producing an output via data bus BS1; a ROM 140 for recording a program executed in an operation process performed by central processing unit 144; a RAM 142 providing a memory region for central processing unit 144 to operate; and a high-speed digital interface 146 allowing data input/output between bus BS1 and the outside. For integrated storage device 148 and ROM 140, though not particularly limited thereto, for example, a flash memory may be used into/from which data can be electrically written/read.
After central processing unit 144 performs a process on the data stored in integrated storage device 148 according to an externally-applied instruction, the data is applied to a synthesizer 160.2 through an On Screen Display (OSD) processing portion 130.
Synthesizer 160.2 synthesizes an output of MPEG-AV decoder 110 and an output of On Screen Display processing portion 130, and provides the synthesized result to a video output terminal 164. An output of video output terminal 164 is provided to a display device (not shown).
Digital broadcasting receiving device 2000 further includes an additional sound generator 120 receiving e.g. data of the result of the process performed by central processing unit 144, and generating a sound effect and the like to be output onto a display device (not shown) based on the data stored in integrated storage device 148, to provide the generated sound effect and the like to a synthesizer 160.1; and a PCM decoder 122 receiving the data processed by central processing unit 144, and generating an audio signal based on the data or the like stored in integrated storage device 148, to provide the generated signal to synthesizer 160.1.
Synthesizer 160.1 receives an output of MPEG-AV decoder 110 and outputs of additional sound generator 120 and PCM decoder 122, and providing a synthesized result to audio output terminal 162. The audio signal provided to audio output terminal 162 is output from a display device (not shown) as sound.
It is noted that digital broadcasting receiving device 2000 may have such a configuration, if required, that includes a modem 150 for transmitting/receiving data to/from the outside, and an IC card interface 152 for receiving information from an IC card.
Through high-speed digital interface 146, for example, an external storage device 180 such as an HDD device for a home server and a remote controller (or a keyboard or the like) 182 which is an external input apparatus are connected to data bus BS1.
FIG. 7 is a schematic block diagram for more specifically illustrating the configurations of TS decoders 104.1 and 104.2 shown in FIG. 6. FIG. 7 particularly shows a state where different types of transport streams TS1 and TS2 are input into TS decoders 104.1 and 104.2, respectively.
Each of transport streams TS1 and TS2 includes, besides video and audio signals, for example, so-called “section data” such as electronic program information. TS decoders 104.1 and 104.2 select, under the control of CPU 144, a transport stream in accordance with designation by the user, and separates the section data from the audio and video signals to be provided to MPEG-AV decoder 110, while performing transmission/reception of data to/from respective memories 148.1 and 148.2 in integrated storage device 148.
FIG. 8 is a schematic block diagram for illustrating the configuration of TS decoder 104.1 shown in FIG. 7. TS decoder 104.2 basically has a similar configuration.
Referring to FIG. 8, TS decoder 104.1 includes a TS input processing circuit 1040 performing a synchronization process on the input transport stream to match the operation synchronizing with a TS input clock from a front end with an internal clock (system clock), and thereafter adding information required for a process in an internal circuit to produce an output; a PID filtering circuit 1050 receiving an output of TS input processing circuit 1040, filtering the received output based on a packet ID (PID), and separating the section data from video and audio signals; a section data filtering circuit 1060 receiving and filtering the section data separated by PID filtering circuit 1050 and producing an output to memory 148.1 for temporarily saving the section data; and an A/V data filtering circuit 1060 receiving and filtering the video and audio signals separated by PID filtering circuit 1050 and producing an output toward MPEG-AV decoder 110.
FIG. 9 is a flow chart showing a process performed by CPU 144 to control TS decoder 104.1 shown in FIG. 8.
For PID filtering circuit 1050, CPU 144 sets a PID for a packet on which a filtering process is to be performed. PID filtering circuit 1050 selects a packet based on the set PID.
FIG. 10 is a schematic block diagram for illustrating the configurations of TS input processing circuit 1040 and PID filtering circuit 1050 shown in FIG. 8.
Referring to FIG. 10, TS input processing circuit 1040 includes a synchronization establishment circuit 1042 receiving transport stream signal TS provided by PSK demodulation circuit 102.1 at the front end, a synchronization signal SYNC indicating a starting position of transport stream signal TS, and a valid signal VALID indicating that input transport stream signal TS is a normal signal in accordance with a reception state and the like, and operating based on the TS input clock provided from the front end, to synchronize transport stream signal TS; an asynchronous data handling circuit 1044 receiving the TS input clock (normally at a few MHz) and an internal processing clock for synchronizing the operation of the internal circuit (normally at several tens of MHz), to synchronize a signal output from synchronization establishment circuit 1042 with the internal processing clock; and an internal circuit requiring information adding circuit (hereinafter referred to as information adding circuit) 1046 receiving an output of asynchronous data handling circuit 1044 and producing an output with addition of TS information required in the subsequent processes.
Here, when signal SYNC is supplied from the front end of digital broadcasting receiving device 2000 as described above, synchronization establishment circuit 1042 establishes synchronization for transport stream signal TS based on the supplied signal SYNC. By contrast, when no signal SYNC is supplied, i.e., for example, when transport stream signal TS is supplied from external storage device 180 or the like, the synchronization establishment process is performed based on a synchronizing signal in transport stream signal TS.
Information adding circuit 1046 operates in response to the internal processing clock, and adds to signal TS, for example, signals BYTE1 to BYTE4 each indicating which one of four bites of the header in transport stream signal TS provided by 188 bytes is output, and signals ADAP and PAY indicating that the output signal is either one of a signal of an adaptation field and a signal of a payload, respectively.
PID filtering circuit 1050 includes a PID determination circuit 1052 operating in response to the internal processing clock, to receive signal TS, signals BYTE1 to BYTE4, and signals ADAP and PAY, and to output a PID adaptation signal indicating which one of section filtering circuit 1060 and A/V data filtering circuit is adapted to the output signal.
As described above with reference to FIGS. 6 to 10, in the conventional digital broadcasting receiving device 2000, an independent TS decoder must be provided for each transport stream in order to accommodate different types of transport streams. Therefore, when the number of transport streams to be handled increases, the number of independent TS decoders must also be increased accordingly, causing a problem of larger circuit scale or the like. Moreover, when a receiver is formed with a circuit scale in a prescribed range, a limitation is set for the number of transport streams that can be handled.
FIG. 11 is a schematic block diagram showing another configuration of a TS decoder in a digital broadcasting receiving device for accommodating different types of transport streams.
In the configuration shown in FIG. 11, a TS selector circuit 105 is provided, at the preceding stage of TS decoder 104.1, for selecting a required TS from a plurality of input TSs, under the control of CPU144.
Such a configuration allows provision of only one independent TS decoder even if different types of transport streams must be handled. However, a problem remains in that TS selector circuit 105 must be separately provided.